1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same in which one of the electrode region is formed in a recess or a trench of a substrate.
2. Background of the Related Art
As the integration of semiconductor devices increases, the width of a gate becomes narrower, and thus, the length of a channel shortens. Therefore, the electric field in the vicinity of a drain is increased to accelerate carriers of the channel region in a depletion layer near the drain during the operation of a device, thereby causing a hot-carrier effect of injecting the carriers into a gate oxide film. The carriers injected into the gate oxide film create static charges in the interface between a semiconductor substrate and the gate oxide film, thereby varying a threshold voltage (V.sub.TH) or reducing a mutual inductance to deteriorate the device characteristics. Accordingly, in order to decrease the degradation of the device characteristics caused by the hot-carrier effect, a lightly doped drain (LDD) structure is used.
FIG. 1 is a cross-sectional view of a related art semiconductor device in which, on a predetermined part of a P-type semiconductor substrate 11, a device isolation region 13 for defining an active region of the device is formed by a local oxidation of silicon (LOCOS) method. A gate 17 is formed on a predetermined part of the active region of semiconductor substrate 11, with a gate insulating film 15 imposed therebetween. A capping oxide film 19 is formed on gate 17. A sidewall 23 is formed on the sides of both gate 17 and capping oxide film 19.
The semiconductor substrate 11 is doped on both sides of gate 17 with a low concentration of N-type impurity, thereby forming a low concentration region 21 for the LDD structure. Further, the semiconductor substrate is doped with a high concentration of N-type impurity so as to be partially overlapped with low concentration region 21, thereby forming source and drain regions 25 and 27, respectively. Source and drain regions 25 and 27 are formed using capping oxide film 19 and sidewall 23 as a mask. Low concentration region 21 is located between source and drain regions 25 and 27 and gate 17.
However, according to the aforementioned related art semiconductor device, low concentration region 21 for the LDD structure is formed in source region 25 as well as in drain region 27, so that the source resistance is increased thereby causing the current characteristics of the device to deteriorate. Further, if the bias of drain region 27 increases, a depletion region is increased, thereby causing a drain-induced barrier lowering (hereinafter, referred to as "DIBL") phenomenon that reduces the potential barrier of the source. In addition, due to the limitations of a photolithographic methods, reduction of the gate width is difficult.